1. Field of the Invention
The present invention relates to a digital phase comparing circuit, and in particular, relates to a phase comparing circuit for preventing an erroneous operation of a next circuit connected thereto when a metastable phenomenon occurs.
Priority is claimed on Japanese Patent Application No. 2007-059091, filed Mar. 8, 2007, the contents of which are incorporated herein by reference.
2. Description of the Related Art
FIG. 4 is a general circuit diagram of a DLL (delay locked loop) used in a DDR SDRAM (double data rate synchronous dynamic RAM) or the like, and FIG. 5 shows the corresponding operation waveforms.
An external clock (signal) CLK, input into an input circuit 1, is transformed into an output control clock CLK0 via a delay circuit 2 and a buffer 3. Based on the clock CLK0, data DQ and a data control clock DQS are respectively output from a DQ output circuit 4 and a DQS output circuit 5. In this process, the delay time with respect to the delay circuit 2 is controlled by a phase comparing circuit 7 and a delay control circuit 8 so that the rising edge of a control clock signal RCLK, output from a dummy circuit 9, coincides with the rising edge of the input clock CLK. Accordingly, the timings of the output data DQ and the clock DQS coincide with the timing of the input clock CLK.
The phase comparing circuit 7 outputs a signal UP, which is (i) L (low) when the control clock signal RCLK rises after the rise of the external clock CLK (see the first half (on the left side) of FIG. 5), and (ii) H (high) when the control clock signal RCLK rises before the rise of the external clock CLK (see the second half (on the right side) of FIG. 5). The delay control circuit 8 receives the UP signal (H or L), and increases or decreases the delay time in accordance with the rising edge of a timing signal CCLK. In FIG. 5, the increase/decrease of the delay time is exaggerated in convenience of the explanations.
FIG. 6 shows the structure of the conventional phase comparing circuit 7, and FIG. 7 shows corresponding operation waveforms.
An edge-trigger D-FF (delay flip-flop) 11 transmits data at the data terminal D to the output terminal Q at the rising edge of a signal input into the clock terminal CK. That is, in the first D-FF 11 on the left side of FIG. 6, an external clock signal CLK is connected to data terminal D, and the control clock signal RCLK is connected to the clock terminal CK, wherein the external clock signal CLK is latched at the rising edge of the control clock signal RCLK. Generally, in the D-FF, when the transition timing at the data terminal D is sufficiently close to the rising edge of the signal at the clock terminal CK, a metastable phenomenon in which the signal output from the output terminal Q oscillates for a specific period may occur (see the second half of FIG. 7). When the bandwidth of the D-FF is relatively narrow, the signal output from the output terminal Q may not oscillate, but a metastable phenomenon, in which the signal output from the output terminal Q becomes unstable while keeping the center value, may occur. The following explanation is applicable to either case. In particular, with respect to the phase comparing circuit of a DLL, the DLL operates so that the rising edge of the control clock signal RCLK becomes closer to the rising edge of the external clock signal CLK, thereby increasing the possibility of an occurrence of the metastable phenomenon.
In a circuit for solving this problem, as shown in FIG. 6, the signal output from the D-FF 11 is applied via an inverter 12 to the data terminal of a D-FF 13, and the control clock signal RCLK is delayed by a time d1 by means of a delay circuit 14, and then applied as a signal UPCLK to the clock terminal CK of the D-FF 13, so that the signal output from the first D-FF 11 is latched by the second D-FF 13 after the delay time d1 has elapsed. That is, positive feedback is applied so as to prevent the signal from being affected by the above-described signal oscillation. The metastable phenomenon is a probability event, and the occurrence probability decreases in inverse proportion to an exponential function with respect to the duration time tMET (see FIG. 7) of the metastable phenomenon. That is, the occurrence probability is decreased by providing a sufficient amount of delay time d1 (between the two D-FFs 11 and 13) to a low value which can actually be disregarded (see, for example, Japanese Unexamined Patent Application, First Publication No. 2005-228426).
However, in recent years, the operation frequency of DRAMs has increased rapidly, and thus it is difficult to provide a sufficient amount of delay time d1. That is, if the delay time d1 is reduced in inverse proportion to the operation frequency so as to provide a sufficient operation margin, the occurrence probability of the metastable phenomenon rapidly increases. That is, as shown in the second half of FIG. 7, if the delay time d1 becomes shorter than the metastable duration time tMET, the relevant oscillation cannot be sufficiently reduced by using the second D-FF 13, which may cause an erroneous operation of the delay control circuit 8 (see FIG. 4)